FPGA Logic Analyzer

FPGA-based Logic Emulators

Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators Jonathan Babb, Russell Tessier, and Anant Agarwal MIT Laboratory for Computer Science Cambridge, MA 02139 Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 to U) percent). This resource imbalance increases the number of chips needed to emulate a...

Testing of FPGA Logic Cells

TerminWeb: Termination Analyzer for Logic Programs

The TerminWeb analyser is a semantic based termination analyser for logic programs. It is uniqueness in that it is based on a semantics which makes the termination properties observable. Its implementation is obtained as an abstraction of an interpreter which computes the termination semantics of a given program. TerminWeb supports termination checking and inference with respect to semi-linear ...

MulVAL: A Logic-based Network Security Analyzer

To determine the security impact software vulnerabilities have on a particular network, one must consider interactions among multiple network elements. For a vulnerability analysis tool to be useful in practice, two features are crucial. First, the model used in the analysis must be able to automatically integrate formal vulnerability specifications from the bug-reporting community. Second, the...

Lightweight Specialized 3-Valued Logic Shape Analyzer

We describe the design and implementation of a specialized shape analysis tool based on 3-valued logic. Our analyzer can reason about programs manipulating recursive data structures, such as singlyand doubly-linked lists, yielding precise results that are comparable to those of the wellknown reference implementation, in only a fraction of the time. In particular, (a) we apply a new and effectiv...